Although technically referring to a semiconductor device having a metal gate electrode and an oxide gate insulator, the term “MOS transistor” is now commonly utilized (and is utilized herein) to refer to any semiconductor device including a conductive gate electrode (whether metal or other conductive material) positioned over a gate insulator (whether oxide or other insulator), which is, in turn, positioned over a semiconductor substrate. The gain of a MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility (μ) of the majority carrier in the transistor channel. The current carrying capacity, and hence the performance of a MOS transistor, is proportional to the mobility of the majority carrier in the channel. The mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor, can be enhanced by applying compressive stress to, and thereby inducing compressive strain within, the silicon of the PMOS channel region. Conversely, the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor, can be increased by applying tensile stress to, and thereby inducing a tensile strain within, the silicon of the NMOS channel region. Conventionally-known stress engineering methods are capable of greatly enhancing transistor performance by improving drive current and switching speed without increasing device size and capacitance. In addition, it is known that the threshold voltage of a particular type of transistor (e.g., PMOS transistors) can be adjusted by embedding strain materials (e.g., silicon germanium) within the transistor channel regions.
Semiconductor manufacturers have expressed increasing interest in the usage of tensile strained silicon-on-insulator (SOI) substrates, which include a layer of tensile strained silicon disposed over an electrically-insulative oxide layer supported by a silicon carrier wafer. In addition to providing the benefits generally associated with SOI substrates (e.g., lower parasitic capacitances, higher operational speeds, and higher integration densities), strained SOI substrates enable relatively high levels of tensile stress to be introduced directly into the channel regions of an integrated circuit's NMOS transistors in an efficient and uniform manner. However, if utilized in conjunction with tensile strained SOI substrates, the above-described techniques for adjusting the threshold voltage of the PMOS transistors by embedding epitaxially-grown SiGe within the transistor channel region are rendered less effective, if not wholly ineffective. In particular, if grown over tensile strained silicon, the SiGe layer will form in a bi-axially expanded state to accommodate the larger lattice constant of the tensile strained silicon. The compressive strain typically imparted to the epitaxially-grown SiGe layer will thus be significantly reduced, and little to no threshold voltage shift will be realized for any PMOS transistor ultimately fabricated over the SiGe layer. This is especially problematic in the case of PMOS transistors incorporating high-k/metal gate stacks, which generally require significant shifts in threshold voltage to enable the usage of metals capable of withstanding the high thermal budgets typically entailed by conventional integrated circuit process flows.
It would thus be desirable to provide methods for fabricating integrated circuits on tensile strained substrates, which enable compressively-strain materials to be introduced into the PMOS transistor channels to, for example, achieve strong threshold voltage shifts enabling or facilitating the usage of high-k/metal gate stacks. More generally, it would be desirable to provide methods for fabricating integrated circuits on strained substrates, whether tensile strained or compressively-strained, allowing strain material having an orientation opposite that of the strained substrate to be incorporated into the channels of a particular type of transistor, whether PMOS or NMOS, to optimize carrier mobility, drive current, and threshold voltage of all transistors included within the integrated circuit. Finally, it would be desirable to provide embodiments of an integrated circuit produced in accordance with such a method. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Technical Field and Background.